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Dataset results
14 results for “FPGA”
Simulation of an imaging calorimeter to demonstrate GarNet on FPGA
<p>This data set is an output of a simulation of electrons and pions shot at a chunk of an imaging calorimeter. It is used in the case study for GarNet-on-FPGA, documented in <a href="https://arxiv.org/abs/2008.03601">arXiv:2008.03601</a>.</p> <p>Each HDF5 file contains the following arrays:</p> <p> Name | Shape | Description</p> <ul> <li>cluster | (10000, 128, 4) | Samples for training and inference. Outermost dimension is the event (cluster). Each cluster has maximum 128 hits, each of which has four features: x, y, z, and energy. The coordinates of the hits are in cm. The energy is in GeV. The x and y coordinates are relative to the seed hit, while the z coordinate is with respect to the calorimeter front face.</li> <li>size | (10000) | Number of hits in each cluster. The cluster array is zero-padded when the cluster size is below 128.</li> <li>truth_pid | (10000) | Identity of the primary particle (0: electron, 1: pion).</li> <li>truth_energy | (10000) | True energy of the primary particle.</li> <li>raw | (10000, 4375, 2) | Raw data (actual output of the simulation). For each event (outermost dimension), hit energy and primary fraction (innermost dimension indices 0 and 1) are given for each of the 4375 sensors. Energy is in MeV.</li> <li>coordinates | (4375, 3) | The x, y, and z coordinates of the 4375 sensors, to be used to interpret the raw data.</li> </ul> <p>See the paper for the details of the simulation.</p>
Tone Discriminator Evolved on iCE40 FPGA
<p>Data created by an experiment that evolved a tone discriminator on an iCE40 FPGA. The experiment was originally conducted by Adrian Thompson on an Xilinx XC6200 FPGA in 1997. This is the reproduction on a modern FPGA.</p> <p> </p> <p>The tone discriminator is a circuit on the FPGA that creates a 3.3 V output signal if presented with a 10 kHz square wave input and a 0 V output signal for a 1 kHz input signal. The circuit was evolved with a Genetic Algorithm and evaluated in three ways:</p> <ol> <li>Clamping: Iterative process to evaluate which cells in the circuit contribute dynamically to the output. A random cell is chosen a and its output set to a random constant value. Afterwards the fitness of the circuit is measured. If it decreases by less than 1 %, the cell is kept clamped, else reset to its original state.</li> <li>Temperature dependence: The FPGA with the circuit was cooled or heated to different temperatures and presented with different input frequencies. The output was averaged over 5 s.</li> <li>Location dependence: The circuit was moved to a different location o the FPGA. The Genetic Algorithm was then continued for additional 200 generations.</li> </ol> <p> </p> <p>This upload contains four groups of files:</p> <ol> <li>experiment.h5 <ul> <li>All measurements and chromosomes from the original run of the Genetic Algorithm</li> </ul> </li> <li>clamping.h5 <ul> <li>All measurements of the clamping process</li> </ul> </li> <li>temperature-XX.h5 <ul> <li>All measurements for a different temperature</li> <li>XX is the temperature in degree Celsius</li> </ul> </li> <li>new_location-X.h5 <ul> <li>All measurements and chromosomes for the continued Genetic Algorithm at a new location on the FPGA</li> <li>X is the running number for hundred generations in the file, e.g. 2 contains generations 101 to 200</li> </ul> </li> </ol> <p> </p> <p> </p> <p>Errata:</p> <ul> <li>The timestamps for the temperature measurements are missing in all files but experiment.h5.</li> </ul> <p> </p>
REASSURE (H2020 731591) Dataset FPGA AES128
<p>This dataset contains 1M of power traces collected on a FPGA hardware implementation of the AES128 block cipher.</p>
Dataset for: "Reducing OpenMP to FPGA Round-trip Times with Predictive Modelling"
<p>This archive contains the samples generated for the conference paper "Reducing OpenMP to FPGA Round-trip Times with Predictive Modelling" (In Proc. 18th Intl. Workshop on OpenMP (IWOMP), Chattanooga, TN, Sept. 2022, Springer LNCS vol. 13527, pp. 94–108, <a href="https://doi.org/10.1007/978-3-031-15922-0_7">https://doi.org/10.1007/978-3-031-15922-0_7</a>).</p> <p><strong>Abstract:</strong> Recent works aimed at expanding the target offloading capabilities of OpenMP to FPGA platforms. While enabling the easy construction of heterogeneous systems, the approach has to face a major hurdle: by blurring the line between software and hardware development, it forces software developers to consider hardware limitations. This can be difficult through the abstractions that OpenMP introduces over the generated hardware. The high level synthesis tools used by OpenMP compilers to generate hardware already offer predictions on hardware usage. Their value for OpenMP offloading however is questionable. This paper is based on the data mining we conducted on thousands of kernel variations. It demonstrates and proofs under which circumstances these predictions can be trusted in the context of OpenMP to FPGA offloading and concludes by showing how to derive runtime performance predictions from them. The model we present can be used without experience in hardware development and quickly predicts runtime on our benchmarks with an average Pearson correlation of 0.897. This knowledge allows developers to make fast, informed design decisions.</p>
Golden-reference and data-under-attack from TRNG on FPGA
<p>This dataset consists of the raw output from an elementary TRNG on a Xilinx Spartan-6 FPGA. The first group of data is called golden-reference. And the second group is called data-under-attack and was collected with an oversampled clock rate.</p>
HPCC FPGA Evaluation Data
<p>This archive contains configuration files, scripts, and full FPGA bitstreams for the execution of the HPCC FPGA benchmarks over multiple FPGAs. Moreover, the raw output files of the measurements are also provided. </p> <p>Update 1.1: Add build configuration, scripts, and output files of additional experiments.</p> <p>Update 1.2: Add artifacts for Xilinx Alveo U280</p>
Dataset supplementing journal article "Design of an FPGA-Based Controller for Fast Scanning Probe Microscopy" in Sensors 2024
<p>Dataset supplementing journal article "Design of an FPGA-Based Controller for Fast Scanning Probe Microscopy" in Sensors 2024.</p> <p>Fast imaging measurements showed in Figure 9 of the article: </p> <p>9a: Fast STM of a static Pt5 cluster on a Fe3O4(001) magnetite surface, taken at room temperature in a UHV chamber with an Omicron VT-AFM microscope at 4 frames/s; pixel resolution 100x100 pixels; image size 8x8 nm2.</p> <p>9b: Fast STM of a Pd-octaethylporphyrin monolayer on a Au(111) surface under electrolyte (phosphate buffer, pH= 7, Ar-saturated), taken with a Beetle-type EC-STM at 12 frames/s (EWE = +0.65 vs RHE, Ub = +0.4 V vs WE); pixel resolution 120x120 pixels; image size 8x8 nm2.</p> <p>9c: Fast AFM images of a Mikromasch TGX1 test grating with a 3 μm pitch and a 130 nm height, taken in contact mode with an Asylum Research/Oxford Instruments MFP-3D microscope (Mikromasch NSC36 probe - 0.6 N/m cantilever) at 4 frames/s; pixel resolution 100x100 pixels.</p>
Supporting data for "KAPow: High-accuracy, Low-overhead Online Per-module Power Estimation for FPGA Designs"
<p>Supporting data for "KAPow: High-accuracy, Low-overhead Online Per-module Power Estimation for FPGA Designs"</p>
Dataset underlying publication "Optical-comb-based frequency stability transfer across the spectrum with a multi-channel FPGA
<p>This archive contains datasets underlying plots of the publication "Optical-comb-based frequency stability transfer across the spectrum with a multi-channel FPGA".</p> <p>Datasets contain header, and a minimum script to reproduce figures is provided</p> <p>This work was supported by the European Metrology Program for Innovation and Research (EMPIR), Project 20FUN08 Nextlasers, which<br>received funding from the EMPIR programme cofinanced by the Participating States and from the European Union’s Horizon 2020 research and innovation program. </p>
Logic Shrinkage: Learned FPGA Netlist Sparsity for Efficient Neural Network Inference [Artefact Evaluation]
<p>Source code of paper "Logic Shrinkage: Learned FPGA Netlist Sparsity for Efficient Neural Network Inference" submitted to FPGA'22 for artefact evaluation.</p>
Supporting data for "KOCL: Power Self-awareness for Arbitrary FPGA-SoC-accelerated OpenCL Applications"
<p>Supporting data for "KOCL: Power Self-awareness for Arbitrary FPGA-SoC-accelerated OpenCL Applications"</p>
Ultra-low power logic in memory with commercial grade memristors and FPGA-based smart-IMPLY architecture
<p>This repository contains the dataset relative to the publication: <em>L. Benatti, T. Zanotti, P. Pavan, and F. M. Puglisi, “Ultra-low power logic in memory with commercial grade memristors and FPGA-based smart-IMPLY architecture,” Microelectronic Engineering, vol. 280, p. 112062, Aug. 2023, doi: <a href="https://doi.org/10.1016/j.mee.2023.112062">10.1016/j.mee.2023.112062</a>.</em></p> <p>In this folder, you will find MATLAB workspaces containing:</p> <ul> <li><strong>caratterizzazione_rram:</strong> The measured values of resistances (LRS and HRS) of the three SDC-memristors used for validating the SIMPLY architecture. The stability of these memristors has been validated over multiple cycles, as shown in Figure 7b.</li> <li><strong>energia_operazioni:</strong> The experimental values of energy versus time (pulse amplitude) for individual operations of SIMPLY, depicted in Figure 9.</li> </ul>
Trunk and Grape detection using DPU's FPGA and Vitis-AI
<p>A series of videos showing up the detection of trunks and grapes in natural vineyards</p>
Nextlasers WP4 - FPGA control for comb-assisted frequency transfer
<p>This dataset contains the VHDL and Matlab code developed in Nextlasers WP4 - frequency transfer using a comb</p> <p> </p> <p>This work was partly supported by the European Metrology Program for Innovation and Research (EMPIR), Project 20FUN08 NextLasers, which received funding from the EMPIR programme cofinanced by the Participating States and from the European Union's Horizon 2020 research and innovation program. </p> <p> </p>
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