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2 results for “Voltage Integration”
Voltage-tunable optical parametric oscillator with an alternating dispersion dimer integrated on chip
<p>With this commit we present or theoretical and experimental data together with plotting codes for our manuscript entitled "Voltage-tunable optical parametric oscillator with an alternating dispersion dimer integrated on chip".</p> <p>Optical parametric oscillators enable the conversion of pump light to new frequency bands using nonlinear optical processes. Recent advances in integrated nonlinear photonics have led to the creation of compact, chip-scale sources via Kerr nonlinearity-induced parametric oscillations. While these sources have provided broadband wavelength tuning, the ability to tune the emission wavelength via dynamically altering the dispersion, has not been attained so far. Here we present a voltage-tunable, on-chip integrated optical parametric oscillator based on an alternating-dispersion dimer, allowing us to tune the emission over nearly 20 THz near 1550 nm. Unlike previous approaches, our device eliminates the need for a widely tunable pump laser source and provides efficient pump filtering at the drop port of the auxiliary ring. Integration of this scheme on a chip opens up the possibility of compact and low-cost voltage-tunable parametric oscillators with diverse application possibilities.</p>
Data: set for "Low-voltage 2D materials-based printed field-effect transistors for integrated digital and analog electronics on paper"
<p>The file reports the raw data of Figure 2, Figure 3 and Figure 4 of the manuscript. Data shown in Figure 2 represent the electrical characterization of the MoS<sub>2</sub> FETs with inkjet-printed silver contacts. Figure 2a is a typical transfer characteristic measured as a function of the gate voltage for a drain voltage of 2.0 V; Figure 2b is a typical output characteristic measured at different gate voltages (from V<sub>GS</sub> = 0.0 V to V<sub>GS</sub> = 1.75 V, steps of 0.25 V). Figure 3 represents the electrical characterization of the MoS<sub>2</sub> FETs with inkjet-printed graphene contacts. In particular, a typical transfer characteristic curve measured as a function of the gate voltage for a drain voltage of 2.5 V is shown and a typical output characteristic curves measured at increasing gate voltages (from V<sub>GS</sub> = 0.0 V to V<sub>GS</sub> = 1.75 V, steps of 0.25 V) are reported in Figure 3b and Figure 3c, respectively. Logic gates and current mirror based on MoS2 FETs with inkjet-printed silver contact are presented in Figure 4. Figure 4c shows the output voltage (left axis) and the voltage gain (right axis) of the inverter gate as a function of the input voltage; Figure 4f the output voltage of the NAND gate as a function of the input states (V<sub>IN1</sub>, V<sub>IN2</sub>). Voltage bias is 5 V for both the inverter and the NAND gate; and Figure 4i g the output current of the current mirror as a function of the output voltage for two different values of the reference current.The file reports the raw data of Figure 2, Figure 3 and Figure 4 of the manuscript. Data shown in Figure 2 represent the electrical characterization of the MoS<sub>2</sub> FETs with inkjet-printed silver contacts. Figure 2a is a typical transfer characteristic measured as a function of the gate voltage for a drain voltage of 2.0 V; Figure 2b is a typical output characteristic measured at different gate voltages (from V<sub>GS</sub> = 0.0 V to V<sub>GS</sub> = 1.75 V, steps of 0.25 V). Figure 3 represents the electrical characterization of the MoS<sub>2</sub> FETs with inkjet-printed graphene contacts. In particular, a typical transfer characteristic curve measured as a function of the gate voltage for a drain voltage of 2.5 V is shown and a typical output characteristic curves measured at increasing gate voltages (from V<sub>GS</sub> = 0.0 V to V<sub>GS</sub> = 1.75 V, steps of 0.25 V) are reported in Figure 3b and Figure 3c, respectively. Logic gates and current mirror based on MoS2 FETs with inkjet-printed silver contact are presented in Figure 4. Figure 4c shows the output voltage (left axis) and the voltage gain (right axis) of the inverter gate as a function of the input voltage; Figure 4f the output voltage of the NAND gate as a function of the input states (V<sub>IN1</sub>, V<sub>IN2</sub>). Voltage bias is 5 V for both the inverter and the NAND gate; and Figure 4i g the output current of the current mirror as a function of the output voltage for two different values of the reference current.</p>
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