Joining, electronics & semiconductor

Line edge & width roughness (LER / LWR)

Line edge and line width roughness as 3-sigma deviation along patterned lines.

Modalities:Top-down SEM
SEM of patterned silicon lines showing the rough, wavy edges measured as line-edge roughness
3.4 nm
LWR 3 sigma
24 nm
Correlation length
120
Lines

Example outputs shown for illustration. Numbers depend on your samples and protocol.

Image: NIST, public domain via Wikimedia Commons

What you get

LER (3 sigma)
LWR (3 sigma)
Edge profile
Power spectral density
Per-line table

The measurement, today

Edge roughness is estimated by eye or from a short manual trace. The sampling is too small to be stable, and the number depends on who drew the trace.

What it costs

Roughness that survives to the transistor gate spreads threshold voltage across a die. At advanced nodes it is a direct performance and yield limiter, and it is invisible to a coarse CD measurement.

From image to reviewed result

  1. 1

    Image the lines

    Load top-down SEM images of the patterned lines.

  2. 2

    Extract the edges

    Both edges of each line are traced sub-pixel along the full imaged length.

  3. 3

    Compute deviation

    Edge position deviation gives LER; width deviation gives LWR, each as a 3-sigma value.

  4. 4

    Report the spectrum

    A power spectral density and correlation length accompany the per-line table.

Scope: Computes roughness statistics from detected edges in your image. Values depend on pixel size and edge-detection settings; hold them fixed to compare across samples.

Send a sample image and a measurement goal

We will show the closest ConductVision workflow and flag what needs custom validation for your images.